My open-hardware design for a 1:8 pulse and frequency distribution amplifier is now available from Aivon LTD.

#### Tagfda

1:8 frequency distribution amplifier based on LMH6702 and LMH6609 op-amps.

In particular the power-supply section using a common-mode choke, a Murata BNX025 filter, and low-noise regulators LT1963 and LT3015 seems to work quite well. I also used ferrites (2 kOhm @ 100 MHz) as well as an RC-filter on all supply pins. Perhaps overkill? Performance with the intended AC/DC brick is still to be verified.

Measurements around 10 MHz show a 1 dB compression at over 14 dBm and an IP3 of around 27 to 30 dBm. The gain extends beyond 100 MHz with some gain-peaking.

Some measurements of residual phase-noise with a 3120A phase-meter, at 10 MHz. My earlier distribution amplifier required shielding with aluminium foil as well as powering from a lead-acid battery to achieve a reasonably quiet phase-noise spectrum. These measurements were done with lab power-supplies for +/-12 V to the board and without any shielding.

Finally some measurements of gain vs. frequency with a Rigol spectrum analyzer.

A new distribution amplifier design featuring a 1PPS pulse distribution amplifier (PDA) and a 5/10 MHz frequency distribution amplifier (FDA).

1U 150mm deep rack-enclosure from Schaeffer. Prototype PCBs without soldermask or silkscreen from Prinel. Both the FDA and PDA boards have 1:8 fan-out with 9 BNC (optionally SMA) connectors spaced 16mm apart. The boards fit comfortably side-by side on a 19" rack panel. Some funky BNC-cables with unusually large connectors may not fit side-by-side 16mm apart - a price to pay for the compact design. The plan is to use an +/-12 AC/DC brick power-supply (not shown) which fits in the back of the enclosure.

Detailed posts on the PDA and FDA boards to follow.

I measured the phase-noise of an Ettus OctoClock distribution amplifier. These plots compare it to earlier measurements on an SRS FS710 and a Symmetricom 6502 as well as my own TADD-1 inspired AD8055 prototype.

OctoClock schematic here: http://files.ettus.com/schematics/octoclock/octoclock.pdf

10 MHz clock-distribution chip: http://www.ti.com/lit/ds/symlink/cdce18005.pdf

For time-nuts kind of stuff (H-masers!) the 10 MHz phase-noise doesn't look that great, and there is something funky going on in the AM noise!? The box is powered by a +6 VDC wall-wart PSU which is probably the cause of all those spikes...

The PPS-channels are based on 7404 hex-inverters and look OK. 200ps of skew is equivalent to 4 cm of trace-length (?) - which seems like a lot if there was an effort to minimize it... For a 1 V/ns rise-time pulse 200ps is equivalent to 200mV of DC-offset in either the signal or the counter trigger-level which also seems like a lot?

I wasn't entirely happy with my frequency distribution amplifier prototype measurements, so I decided to do some SPICE simulations.

Here is a circuit close to the original TADD-1 design, configured for a voltage gain of 2, which when loaded with 50R corresponds to unity gain or 0 dB.

The main contribution to the noise floor at 10 MHz is by the AD8055 op-amp (roughly 3/4ths), with the gain-resistors R4 and R5 also contributing (roughly 1/4th). The simulation gives an output-referred noise-floor of 17.4 nV/sqrt(Hz) between around 100kHz and 20MHz. At low frequencies the 1/f noise of the op-amp dominates. The large 47k bias-resistors R2 and R3 are not bypassed/filtered in this design and they contribute significantly at low frequencies.

17.4nV/sqrt(Hz) is -142 dBm/Hz. This is a one-sided spectrum so we subtract 3 dB to get a single-sideband number, and then another 3 dB since noise is divided equally into AM and PN. This gives a best-case PN of -148 dBc/Hz for a 0 dB input/output power. In my measurements I got about -157 dBc/Hz with +7 dBm output.

The v2 design uses the ADA4899-1 op-amp instead of the AD8055. This improves the op-amp input voltage noise floor from 6 nV/sqrt(Hz) to 1 nV/sqrt(Hz) while also reducing the near-DC voltage noise by more than ten-fold.

The simulation for the ADA4899-1 design shows an output-referred noise floor of 4 nV/sqrt(Hz) from 10 kHz to 20 MHz. This corresponds to about -155 dBm/Hz, **a 12.7 dB improvement over the original design**. The SPICE model for the ADA4899-1 does not include 1/f noise so I have estimated it with a dashed line. I have tried to minimize the resistor noise with reduced resistance values for the gain-setting resistors R4, R5, and a bypassed (C5) 'T'-circuit for the DC-bias (R2, R3, R9).

The theoretical PN floor with 0 dBm signal is now -161 dBc/Hz (again 13 dB better than for the original design).

Here is a figure that compares the two simulations:

These figures show an AC sweep response for the SPICE simulations:

Further ideas and ToDo:

- What is the limit for reducing values of R4 and R5? Power-dissipation, current-draw from the op-amp?
- Reduce value of R7 - do we even need it.. (improves isolation between output stages?)
- Replace R9 with an inductor - BUT it creates a resonance with C5 that needs to be damped - probably not worth it.
- Improve on the powersupply schematic in the prototype. Spurs were big with a SMPS +12VDC supply.
- Do PSRR simulations? Does that give different optimization goals for the DC-bias circuit?
- Find an even better op-amp?
- Where do we find a good SPICE model for ADA4899-1? The one I am using has a realistic AC gain response but unrealistic noise model near DC. There is an alternative on the analog.com website with realistic 1/f noise behaviour but infinite AC gain bandwidth!!??

Constructive comments are welcome!

**Update 2015-12-18**: Things improved quite a lot by simply wrapping the board in aluminium foil!

The amplifier phase noise floor is now at around -156 dBc/Hz while the 6502 is at -163 dBc/Hz. The AM noise numbers are similar.

**Original post 2015-12-17:** I put together a first prototype (only one output channel) of my TADD-1 inspired frequency distribution amplifier. Preliminary schematic here.

I compared the prototype board to two commercial distribution amplifiers: an SRS FS710 (quite awful) and a Symmetricom 6502 (very good). I also compared my new data with John Ackermann's measurements from 2007.

The new board showed ugly spurs at 50 Hz and harmonics using an el-cheapo wall-wart 12 VDC SMPS, so I also tried it with an "ultra-low noise DC-source" a.k.a 12 V lead-acid battery.

We need a number of frequency distribution amplifiers in the lab. Let's not reinvent the wheel but rather do a face-lift for the TADD-1. John Ackermann has phase noise measurements on the TADD-1 and TvB has temperature coefficient results on the TADD-1.

Here's a draft design for an SMD version of the TADD-1 frequency distribution amplifier. The plan is for a 2-sided 180 mm x 110 mm PCB. Two of these could be mounted side by side in a 1U 19" enclosure to give 2x8=16 outputs on the front panel. If a companion pulse distribution (1-PPS) board is built, the output at the back of this board can be used to drive a PICDIV on the pulse-distribution board. This gives 8 frequency outputs and 8 pulse outputs on a 1U 19" panel. The 2-pin connector at the DC-input can be used to power the other board in the same enclosure.

Comments? Suggestions?

- What causes phase-noise (drift) below 1Hz offset frequency in this graph?
- The original TADD-1 used a MAX477 and the update in 2007 used an AD8055. Are there newer and better op-amps?
- We need a good low-noise linear regulator circuit (lower right corner). Suggestions? (what's inside an Abracon ABPSM-ULN-A?)

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