Tagdds

AD9912 DDS frequency resolution?

See also discussion on the AD forum: https://ez.analog.com/dds/f/q-a/107510/ad9912-ftw-lsb-always-zero

We've tried to measure the frequency resolution of the AD9912 DDS, which when used with a 1 GHz SYSCLK should be 1 GHz / 2**48 = 3.55 uHz.

We tried an ARTIQ Urukul-board and an AD dev-board and got the following results:

In both cases the output frequency corresponds to an even frequency tuning word (FTW) although we step the frequency by one LSB. In other words the LSB appears to be zero in all cases, even when we write an odd FTW with '1' as the LSB. Instead of the expected 3.55 uHz frequency resolution we see double-sized steps of 7.1 uHz.

The Urukul measurement was done with a Microsemi 3120A phase-meter and the dev-board was measured using a PICDIV 1PPS-divider followed by a Keysight 53230A time interval counter. The even FTW frequencies agree with the predicted frequency to much better than 0.1 uHz.

ADF4350 PLL+VCO and AD9912 DDS power spectra

Update 2015-09-28: ADEV and Phase-noise measured with a 3120A:

 

Here's the 1 GHz output of an ADF4350 PLL+VCO evaluation board, when used with a 25 MHz reference.

The datasheet shows a phase noise of around -100 dBc/Hz @ 1-100 kHz, so this measurement may in fact be dominated by the Rigol DSA1030A phase noise which is quoted as -88 dBc/Hz @ 10 kHz.

1GHz_adf4350_output_with_25MHz_ref-input

The 1 GHz output from the ADF4350 is used as a SYCLK input for an AD9912 DDS. The spectrum below shows a 100 MHz output signal from the DDS with either a 660 MHz or 1 GHz SYSCLK. The 660 MHz SYSCLK is from a 10 MHz reference multiplied 66x by the AD9912 on-board PLL. The 1 GHz SYSCLK is from the ADF4350, with the AD9912 PLL disabled.

The AD9912 output is clearly improved when using an external 1 GHz SYSCLK. The noise-floor drops from -80 dBm to below -90 dBm @ 250 kHz from the carrier. The spurious peaks at +/- 50 kHz disappear. However this result is still far from the datasheet result where all noise is below -95 dBm just a few kHz from the carrier. It shouldn't matter much that the datasheet shows a 200MHz output while I measured a 100 MHz output.

Again I suspect the Rigol DSA1030A's phase-noise performance of -88dBc/Hz @ 10 kHz may in fact significantly determine the shape of the peak. Maybe the real DDS output is a clean delta-peak, we just see it like this with the spectrum analyzer?

100MHz_AD9912_internal_vs_external_PLL

Martein/PA3AKE has similar but much nicer results over here: 1 GHz refclock and 14 MHz output from AD9910 DDS. Amazingly both these spectra show a noise-floor below -90 dBm @ 50 Hz! Maybe it's because the spectrum analyzer used (Wandel & Goltermann SNA-62) is much better?

DDS Front Panel

Two of these 1U 19" rack-enclosure front panels came in from Shaeffer today. Around 70 euros each, and the best thing is you get an instant quote on the front panel while you are designing it with their Front Panel Designer software. The box will house an AD9912 DDS.

dds_panel_0

From left to right: 10 MHz reference frequency input BNC, DDS output BNC, 40mm fan (1824257 and 1545841), 20x2 character LCD (73-1289-ND), rotary encoder with pushbutton (102-1767-ND), and rightmost an Arduino Due (1050-1049-ND) with Ethernet shield (1050-1039-ND). The panel is made to fit a Schroff 1U enclosure (1816030) with the inside PCBs mounted to a chassis plate (1370461).

dds_panel_1

Here's a view from the inside. I milled down the panel thickness from 4 mm to around 2.5 mm on the inside around the rotary encoder. Otherwise all components seem to fit as designed.

dds_panel_2

Next stop is coding an improved user-interface as well as remote-control of the DDS and PLL over Ethernet.

AD9912 DDS Test

Update: it turns out the PLL filter components were not connected at all during the first tests I did 🙂 Here's a picture that compares the schematic against the actual board. When I changed the 0R resistor from position "R3" to position "R5"  the PLL started behaving much more nicely. If anyone from AD is reading - please update your documentation!

ad9912_eval_board_pll_schematic

With this change, and a 66x PLL multiplier giving a 10MHz x 66 = 660 MHz SYSCLOCK I get quite nice output:

Fout100M_Span50M Fout100M_Span400M Fout100M_Span500k

The output is set to 100 MHz and has an amplitude of ~0 dBm. There are -60 dBm spurs at +/- 50 kHz (not sure why?), -70 dBm spurs at +/- 10MHz, and a -65 dBm second harmonic at 200 MHz.

If I activate the "2x Reference" setting which detects both rising and falling edges of the input clock, and use that with a 40x PLL for a 10MHz x2 x40 = 800 MHz SYSCLOCK I still get very strong spurs at 10 MHz:

Fout100M_Span400_PLL_2x40x

I have been testing this AD9912 DDS evaluation board:
ad9912_evkit_pcb_text

So far the results are a bit strange, with output as advertized only when no external input clock is supplied. Strange.

dds_test_2013-12-30

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